RF / DSP Verification Architect

Nasze wymagania: System Verilog RTL architecture design for complex IP High-speed protocols: 100Gb Ethernet, PCIe Gen5, AMBA / AXI FPGA / Adaptive SoC design flow leadership: Synthesis Place & Route (P&R) Timing closure Integration Vivado / Vitis expertise Python / Tcl scripting for automation CI/CD governance and Git workflow standards Proven technical leadership and mentoring experience Zakres obowiązków: Lead IP architecture and RTL design strategy for FPGA and Adaptive SoC platforms Define timing closure methodology and integration approaches Own architectural decisions ensuring scalability, performance, and maintainability Lead FPGA / Adaptive SoC design flows including synthesis, P&R, and integration Oversee implementation of high-speed protocol IP Drive automation and quality standards using scripting and CI/CD governance Provide technical leadership and mentorship to design teams Oferujemy: Location: Poland (Remote / Project-based)