ASIC/FPGA Verification Engineer

Nasze wymagania: at least 2-3 years of relevant experience (verification of ASIC/FPGA using SystemVerilog). we are also open for internships. very good knowledge of English that allows everyday communication and documentation creation, very good understanding of Digital Design principles, very good understanding of SoC, knowledge of SystemVerilog, good knowledge of Object Oriented Programming, ability and willingness to learn and work as part of a team, a valid work permit for Poland/European Union. knowledge of communication interfaces such as I2C, SPI, AHB understanding of configuration management and change management principles, knowledge of scripting languages, experience of using modern simulation tools (Modelsim/Questa, Simvision). Zakres obowiązków: work on projects for the largest players in ASIC world, verify digital circuits using SystemVerilog language and the most modern ASIC verification methodology - UVM, create project documentation for designs certifications, work on a structured and well planned projects (we use Requirements Based Development Processes in our projects). Oferujemy: competitive salary package adequate to competencies, full employment contract, working on challenging projects, support of senior engineers to allow you quickly gain technical experience, partial remote work, very good working atmosphere.